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| general description the max7057 frequency-programmable uhf transmit- ter is designed to transmit ask/fsk data at a wide range of frequencies from 300mhz to 450mhz. the max7057 has internal tuning capacitors at the output of the power amplifier that are programmable for match- ing to an antenna or load. this allows the user to change to a new frequency and match the antenna at the new frequency simultaneously. the max7057 trans- mits at a data rate up to 100kbps nonreturn-to-zero (nrz) (50kbps manchester coded). typical transmitted power into a 50 ? load is +9.2dbm with a +2.7v supply. the device operates from +2.1v to +3.6v and typically draws under 12.5ma of current in fsk mode (8.5ma in ask mode) when the antenna-matching network is designed to operate over the 315mhz to 433.92mhz frequency range. for narrower operating frequency ranges, the matching network can be redesigned to improve efficiency. the standby current is less than 1a at room temperature. the max7057 reference frequency from the crystal oscillator is multiplied by a fully integrated fractional-n phase-locked loop (pll). the multiplying factor of the pll is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction; the multiplying factor can be anywhere between 19 and 28. the 12-bit fraction in the synthesizer sets a tuning resolution equal to the refer- ence frequency divided by 4096; frequency deviation can be set as low as 2khz and as high as 100khz. the fractional-n synthesizer eliminates the problems associated with oscillator-pulling fsk signal generation. the max7057 has a serial peripheral interface (spi?) for selecting all the necessary settings. the max7057 is available in a 16-pin so package and is specified to operate in the -40c to +125c automo- tive temperature range. applications rf remote controls garage door openers home automation automotive wireless sensors wireless game consoles wireless computer peripherals security systems features programmable frequency operation with single crystal internal variable capacitor for antenna tuning with single-matching network 100kbps data rate (nrz) +2.1v to +3.6v single-supply operation < 12.5ma (fsk), < 8.5ma (ask) dc current drain < 1 a standby current ask/fsk modulation 47% carrier tuning range using one crystal max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter ________________________________________________________________ maxim integrated products 1 pin configuration ordering information 19-4093; rev 1; 4/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes a lead(pb)-free package/rohs-compliant package. part temp range pin-package max7057ase+ -40c to +125c 16 so typical application circuit and functional diagram appear at end of data sheet. spi is a trademark of motorola, inc. dgnd din pagnd 1 + 2 dvdd gpo sdi sclk cs top view 3 4 agnd xtal1 xtal2 pavdd avdd 5 enable paout rout 6 7 8 max7057 14 13 16 15 12 11 10 9
max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics ( typical application circuit , 50 ? system impedance, tuned for 315mhz to 433.92mhz operation, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, f crystal = 16mhz, t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted. all min and max values are 100% tested at t a = +125c, and guaranteed by design and characterization over temperature, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, pavdd, avdd, dvdd to agnd, dgnd, pagnd ...................................................-0.3v to +4.0v all other pins..................................._gnd - 0.3v to _v dd + 0.3v continuous power dissipation (t a = +70c) 16-pin so (derate 8.7mw/c above +70c)...............695.7mw operating temperature .....................................-40c to +125c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units supply voltage v dd pavdd, avdd, and dvdd connected to power supply, v dd 2.1 2.7 3.6 v f rf = 315mhz 3.9 6.5 pa off, v din at 0% duty cycle (ask) f rf = 433.92mhz 4.5 7.5 f rf = 315mhz 8.1 15.1 v d in at 50% d uty cycl e ( as k) ( n otes 1, 2, 3) f rf = 433.92mhz 8.5 15.0 f rf = 315mhz 12.2 23.7 supply current i dd v din at 100% duty cycle (fsk) (note 1) f rf = 433.92mhz 12.4 22.4 ma t a = + 25c ( n ote 3) 0.8 t a < + 85c ( n ote 3) 1 6.4 standby current i stdby v enable < v il t a < +125c 6.2 20.1 a digital i/o input high threshold v ih 0.9 x v dvdd v input low threshold v il 0.1 x dv dd v input pulldown sink current 13 a input pullup source current 9a output-voltage high v oh i sink = 500a (gpo) v dd - 0.37 v output-voltage low v ol i source = 500a (gpo) 0.36 v max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter _______________________________________________________________________________________ 3 ac electrical characteristics ( typical application circuit , 50 ? system impedance, tuned for 315mhz to 433.92mhz operation, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, f crystal = 16mhz, t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted. all min and max values are 100% tested at t a = +125c, and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units general characteristics frequency range 300 450 mhz enable transition low-to-high, frequency settled to within 50khz of the desired carrier 120 power-on time t on enable transition low-to-high, frequency settled to within 5khz of the desired carrier 260 s manchester encoded 50 ask mode nonreturn-to-zero 100 manchester encoded 50 maximum data rate fsk mode nonreturn-to-zero 100 kbps frequency switching time time from end of spi write to frequency settled to within 5khz of desired carrier 70 s phase-locked loop (pll) vco gain k vco 320 mhz/v 10khz offset -78 f rf = 315mhz 1mhz offset -98 10khz offset -73 pll phase noise f rf = 433.92mhz 1mhz offset -98 dbc/hz loop bandwidth 300 khz reference frequency input level 500 mv p-p frequency-divider range 19 28 frequency deviation (fsk) 2 100 khz crystal oscillator crystal frequency f xtal 10.71 16 23.68 mhz frequency pulling by v dd 4 ppm/v crystal load capacitance (note 4) 10 pf power amplifier (pa) t a = +25c (note 3) 3.8 9.2 16.4 t a = +125c, v avdd = v dvdd = v pavdd = +2.1v 2.4 5.2 output power (note 1) p out t a = -40c, v avdd = v dvdd = v pavdd = +3.6v (note 3) 12.6 17.0 dbm modulation depth 71 db f rf = 315mhz -29 maximum carrier harmonics with output matching network f rf = 433.92mhz -44 dbc reference spur -45 dbc max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 4 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , 50 ? system impedance, tuned for 315mhz to 433.92mhz operation, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, f crystal = 16mhz, t a = -40c to +125c, unless otherwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted. all min and max values are 100% tested at t a = +125c, and guaranteed by design and characterization over temperature, unless otherwise noted.) parameter symbol conditions min typ max units serial interface (spi) timing characteristics (figure 1) minimum sclk low to falling- edge of cs setup time t sc 10 ns minimum cs low to rising-edge of sclk setup time t css 5ns minimum sclk low to rising- edge of cs setup time t hcs 20 ns minimum sclk low after rising- edge of cs hold time t hs 5ns minimum data valid to sclk rising-edge setup time t ds 10 ns minimum data valid to sclk rising-edge hold time t dh 5ns minimum sclk high pulse width t ch 40 ns minimum sclk low pulse width t cl 40 ns minimum cs high pulse width t csh 40 ns maximum transition time from falling-edge of cs to valid gpo t csg c l = 10pf load capacitance from gpo to dgnd 50 ns maximum transition time from falling-edge of sclk to valid gpo t cg c l = 10pf load capacitance from gpo to dgnd 50 ns note 1: supply current and output power are greatly dependent on board layout and paout match. note 2: 50% duty cycle at 10khz ask data (manchester coded). note 3: guaranteed by design and characterization, not production tested. note 4: dependent on pcb trace capacitance. t sc t hcs t hs t dh t cg t csg t ds t csh t ch t cl t css cs sclk sdi gpo figure 1. spi timing diagram max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter _______________________________________________________________________________________ 5 supply current vs. supply voltage max7057 toc01 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 9 10 11 12 13 14 15 16 17 18 8 2.1 3.6 f rf = 315mhz pa on t a = +25 c t a = -40 c t a = +85 c t a = +125 c supply current vs. supply voltage max7057 toc02 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 6 7 8 9 10 11 12 5 2.1 3.6 f rf = 315mhz 50% duty cycle t a = +25 c t a = -40 c t a = +85 c t a = +125 c supply current vs. supply voltage max7057 toc03 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 2.5 3.0 3.5 4.0 4.5 5.0 6.0 5.5 2.0 2.1 3.6 f rf = 315mhz pa off t a = +25 c t a = -40 c t a = +85 c t a = +125 c supply current vs. supply voltage max7057 toc04 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 9 10 11 12 13 14 15 16 17 18 8 2.1 3.6 f rf = 433.92mhz pa on t a = +25 c t a = -40 c t a = +85 c t a = +125 c supply current vs. supply voltage max7057 toc05 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 6 7 8 9 10 11 12 5 2.1 3.6 f rf = 433.92mhz 50% duty cycle t a = +25 c t a = -40 c t a = +85 c t a = +125 c supply current vs. supply voltage max7057 toc06 supply voltage (v) supply current (ma) 3.3 3.0 2.7 2.4 3.5 4.0 4.5 5.0 5.5 6.0 7.0 6.5 3.0 2.1 3.6 f rf = 433.92mhz pa off t a = -40 c t a = +85 c t a = +125 c t a = +25 c typical operating characteristics (50 ? system impedance, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40c to +125c, unless oth- erwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted.) output power vs. supply voltage max7057 toc07 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 2 4 6 8 10 14 12 0 2.1 3.6 f rf = 315mhz pa on t a = +85 c t a = +125 c t a = +25 c t a = -40 c output power vs. supply voltage max7057 toc08 supply voltage (v) output power (dbm) 3.3 3.0 2.7 2.4 2 4 6 8 10 14 12 0 2.1 3.6 f rf = 433.92mhz pa on t a = +85 c t a = +125 c t a = -40 c, +25 c supply current and output power vs. external resistor max7057 toc09 external resistor ( ? ) supply current (ma) output power (dbm) 1000 100 10 1 2 4 6 8 10 14 12 0 -15 -10 -5 0 5 15 10 -25 -20 0.1 10,000 f rf = 315mhz pa on supply current output power max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 6 _______________________________________________________________________________________ typical operating characteristics (continued) (50 ? system impedance, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40c to +125c, unless oth- erwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted.) supply current and output power vs. external resistor max7057 toc10 external resistor ( ? ) supply current (ma) output power (dbm) 1000 100 10 1 2 4 6 8 9 1 3 5 7 0 -15 -10 -5 0 5 10 -25 -20 0.1 10,000 f rf = 315mhz 50% duty cycle supply current output power supply current and output power vs. external resistor max7057 toc11 external resistor ( ? ) supply current (ma) output power (dbm) 1000 100 10 1 2 4 6 8 10 14 12 0 -15 -10 -5 0 5 15 10 -25 -20 0.1 10,000 f rf = 433.92mhz pa on supply current output power supply current and output power vs. external resistor max7057 toc12 external resistor ( ? ) supply current (ma) output power (dbm) 1000 100 10 1 2 4 6 8 9 1 3 5 7 0 -15 -10 -5 0 5 10 -30 -20 0.1 10,000 f rf = 433.92mhz 50% duty cycle supply current output power -25 max7057 toc13 phase noise vs. offset frequency -60 -70 -80 -90 -100 -110 -120 -130 -140 100 10k 100k 1m 10m 1k offset frequency (hz) phase noise (dbc/hz) f rf = 315mhz -50 -60 -70 -80 -90 -100 -110 -120 -130 100 10k 100k 1m 10m 1k phase noise vs. offset frequency max7057 toc14 offset frequency (hz) phase noise (dbc/hz) f rf = 433.92mhz -60 -50 -55 -40 -45 -35 -30 2.1 3.6 reference spur magnitude vs. supply voltage max7057 toc15 supply voltage (v) reference spur magnitude (dbc) 2.7 2.4 3.0 3.3 f rf = 433.92mhz f rf = 315mhz max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter _______________________________________________________________________________________ 7 typical operating characteristics (continued) (50 ? system impedance, v avdd = v dvdd = v pavdd = +2.1v to +3.6v, f rf = 300mhz to 450mhz, t a = -40c to +125c, unless oth- erwise noted. typical values are at v avdd = v dvdd = v pavdd = +2.7v, t a = +25c, unless otherwise noted.) efficiency vs. supply voltage max7057 toc18 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 13 11 17 21 25 9 15 19 23 2.1 3.6 f rf = 315mhz 50% duty cycle t a = +85 c t a = +125 c t a = +25 c t a = -40 c efficiency vs. supply voltage max7057 toc19 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 15 20 25 30 35 10 2.1 3.6 f rf = 433.92mhz pa on t a = +85 c t a = +125 c t a = +25 c t a = -40 c efficiency vs. supply voltage max7057 toc20 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 11 13 15 17 19 21 23 9 2.1 3.6 f rf = 433.92mhz 50% duty cycle t a = +85 c t a = +25 c t a = +125 c t a = -40 c -76 -56 -66 -36 -46 -16 -26 -6 +14 +4 +24 fsk spectrum max7057 toc21 (dbm) 100khz deviation, 4khz square-wave modulation. span = 1.00mhz rbw = 10khz vbw = 10khz video avg on -10 -4 -6 -8 -2 0 2 4 6 8 10 2.1 2.7 2.4 3.0 3.3 3.6 frequency stability vs. supply voltage max7057 toc16 supply voltage (v) frequency stability (ppm) f rf = 433.92mhz f rf = 315mhz efficiency vs. supply voltage max7057 toc17 supply voltage (v) efficiency (%) 3.3 3.0 2.7 2.4 15 20 25 30 35 10 2.1 3.6 f rf = 315mhz pa on t a = +85 c t a = +125 c t a = +25 c t a = -40 c max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 8 _______________________________________________________________________________________ pin description pin name function 1 cs serial interface active-low chip select. internally pulled up to dvdd. 2 sdi serial interface data input. internally pulled down to gnd. 3 sclk serial interface clock input. internally pulled down to gnd. 4 pagnd power amplifier ground 5 paout power amplifier output. requires a pullup inductor to the supply voltage or rout. the pullup inductor can be part of the output-matching network. 6rout envelope-shaping output. rout controls the power amplifier envelopes rise and fall times. connect rout to the pa pullup inductor or to an optional power-adjust resistor. bypass the inductor to gnd as close as possible to the inductor with 680pf and 220pf capacitors. 7 pavdd power amplifier supply voltage. bypass to ground with 0.01f and 220pf capacitors placed as close as possible to the pin. 8 avdd analog positive supply voltage. bypass to ground with 0.1f and 0.01f capacitors placed as close as possible to the pin. 9 xtal2 crystal input 2. xtal2 can be driven from an ac-coupled external reference. 10 xtal1 crystal input 1. bypass to ground if xtal2 is driven from an ac-coupled external reference. 11 agnd analog ground 12 enable enable pin. drive high for normal operation; drive low or leave unconnected to put the device in standby mode. internally pulled down to gnd. 13 din ask/fsk data input. use the control register (address: 0x00) to select the type of modulation. internally pulled down to gnd. 14 dgnd digital ground 15 gpo general-purpose output. can be configured to output various digital signals (spi serial data outputsdo, clkoutreference oscillator frequency divided by 1, 2, 4, or 8 for microprocessor clock, etc). 16 dvdd digital positive supply voltage. bypass to ground with 0.1f and 0.01f capacitors placed as close as possible to the pin. detailed description the max7057 is frequency programmable from 300mhz to 450mhz, by using a fractional-n phase-locked loop (pll), and transmits data using either ask or fsk mod- ulation. the max7057 has integrated tuning capacitors at the output of the power amplifier (pa) to ensure high- power efficiency at various programmable frequencies with a single-matching network. the crystal-based architecture of the max7057 elimi- nates many of the common problems with saw trans- mitters by providing greater modulation depth, faster frequency settling, tighter transmit frequency tolerance, and reduced temperature dependence. in particular, the tighter transmit frequency tolerance means that a superheterodyne receiver with a narrower if bandwidth (therefore lower noise bandwidth) can be used. the payoff is better overall receiver performance when using a superheterodyne receiver such as the max1471, max1473, max7033, max7034, or max7042. frequency programming the max7057 is a crystal-referenced phased-locked loop (pll) vhf/uhf transmitter that transmits data over the frequency range of 300mhz to 450mhz in ask or fsk mode. the transmit frequency is set by the crystal frequency and the programmable divider in the pll; the programmable-divide ratios can be set anywhere from 19 to 28, which means that with a crystal frequen- cy of 16mhz, the output frequency range can be from 304mhz to 448mhz. the fractional-n architecture of the pll in the max7057 allows the fsk signal to be programmed for exact fre- quency deviations and rapid, transient-free frequency settling time. this modulation method completely elimi- nates the problems associated with crystal-pulling fsk signal generation. the multiplying factor of the pll is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction. the 12-bit fraction in the synthesizer results in a tuning resolution that is equal to the refer- ence frequency divided by 4096. the max7057 has an internal variable shunt capacitor connected at the pa output. this capacitor is controlled using the spi to maintain highly efficient transmission at any frequency within a 1.47 to 1 (28/19) tuning range. this means that it is possible to change the frequency and retune the antenna to the new frequency in a very short time. the combination of rapid-antenna tuning ability with rapid-synthesizer tuning makes the max7057 a true frequency-agile transmitter. the tuning capacitor has a resolution of 0.25pf. the max7057 also features adjustable output power through an exter- nal resistor to nearly +10dbm into a 50 ? load at +2.7v. the max7057 supports data rates up to 100kbps nrz in both ask and fsk modes. in fsk mode, the fre- quency deviation can be programmed as low as 2khz and as high as 100khz. power amplifier (pa) the pa of the max7057 is a high-efficiency, open-drain switching-mode amplifier. in a switching-mode amplifi- er, the gate of the final-stage fet is driven with a very sharp 25% duty-cycle square wave at the transmit fre- quency. this square wave is derived from the synthe- sizer circuit. when the matching network is tuned correctly, the output fet resonates the attached match- ing circuit with a minimum amount of power dissipated in the fet. with a proper output-matching network, the pa can drive a wide range of antenna impedances, which include a small-loop pcb trace and a 50 ? anten- na. the output-matching network suppresses the carri- er harmonics and transforms the antenna impedance to an optimal impedance at paout, which is from 125 ? to 250 ? . when the output-matching network is properly tuned, the pa transmits power with a high overall efficiency of up to 25%. the efficiency of the pa itself is more than 39%. the output power can be adjusted by changing the impedance seen by the pa or by adjusting the value of an external resistor at paout. envelope shaping the max7057 features an internal envelope-shaping resistor for ask modulation, which connects between pavdd and rout. when connected to the pa pullup inductor, the envelope-shaping resistor slows the turn- on/-off time of the pa and results in a smaller spectral width of the modulated pa output signal. variable capacitor the max7057 has a set of internal variable shunt capacitors that can be switched in and out to present different capacitor values at the pa output. the capaci- tors are connected from the pa output to ground. this allows changing the tuning network along with the syn- thesizer divide ratio each time the transmitted frequency changes, making it possible to maintain maximum trans- mitter power while moving rapidly from one frequency to another. when the particular capacitance control bit is high, the corresponding amount of shunt capacitance is added at paout. the 32 capacitor values are selected using the spi; the capacitance resolution is 0.25pf. the total capacitance can vary from 0 to 7.75pf. for example, if cap[1] and cap[3] are high, and cap[4], cap[2], and cap[0] are low, this circuit will add 2.5pf at paout. see table 1 for variable capacitor values and control bits. fractional-n phase-locked loop (pll) the max7057 utilizes a fully integrated fractional-n pll for its transmit frequency synthesizer. all pll compo- nents, including the loop filter, are included on-chip. the loop bandwidth is programmable to either 300khz or 600khz. see tables 2, 3, and 4 for pllbw bit description. the 16-bit fractional-n topology allows the transmit frequency to be adjusted in increments of f xtal /4096. the allowable range of the f rf /f xtal ratio is approximately 19 to 28. the fractional-n topology also allows exact fsk fre- quency deviations to be programmed, completely elimi- nating the problems associated with generating frequency deviations by crystal oscillator pulling. the integer and fractional portions of the pll divider ratio set the transmit frequency. the following example shows how to determine the correct values to be loaded to registers hifreq1, hifreq0, lofreq1, and lofreq0. see tables 2, 3, and 7C10 for a detailed description of these registers. max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter _______________________________________________________________________________________ 9 table 1. variable capacitor values and control bits spi register bits incremental shunt capacitance (pf) cap[0] 0.25 cap[1] 0.5 cap[2] 1.0 cap[3] 2.0 cap[4] 4.0 max7057 due to the nature of the transmit pll frequency divider, a fixed offset of 16 must be subtracted from the trans- mit pll divider ratio for programming the max7057s transmit frequency registers. to determine the value to program the max7057s transmit frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value: assume that the ask transmit frequency = 315mhz and f xtal = 16mhz. in this example, the rounded deci- mal value is 15,104, or 0x3b00 hexadecimal. the upper 2 bytes (0x3b) are loaded into the lofreq1 register, and the low 2 bytes (0x00) are loaded into the lofreq0 register. in ask mode, the transmit frequen- cy equals the lower frequency programmed into the max7057s transmit frequency registers (see tables 2, 3, and 9C12). in fsk mode, the transmit frequencies equal the upper (hifreq1 and hifreq0) and lower (lofreq1 and lofreq0) frequencies programmed into the max7057s transmit frequency registers. calculate the upper and lower frequency in the same way as shown above. fsk deviations as low as 2khz and as high as 100khz are programmable (see tables 2, 3, and 8C12). the exact min and max values for the transmit frequen- cy registers (hifreq1/0, lofreq1/0) are 2.9596 (0x2f42) and 12.0220 (0xc05a), yielding a synthesizer ratio of 18.9596 and 28.0220, respectively. these limits must be followed to prevent the delta-sigma modula- tor from overflowing. whenever all of the fractional bits in the hifreq1/0 and lofreq1/0 registers are zero (fhi[11:0] and flo[11:0]), only an integer divider is used, and the delta-sigma modulator is not in operation. this allows lower current operation. the 600khz pll bandwidth should be used in this mode to reduce phase noise. any change to the transmit frequency registers must be followed by writing a 1 to the self-reset frequency load register (see tables 2, 3, and 12). crystal (xtal) oscillator the crystal (xtal) oscillator in the max7057 is designed to present a capacitance of approximately 6pf between xtal1 and xtal2. in most cases, this corresponds to an 8pf load capacitance applied to the external crystal when typical pcb parasitics are added. the max7057 is designed to operate with a typical 10pf load capacitance crystal. it is very important to use a crystal with a load capacitance that is equal to the capacitance of the max7057 crystal oscillator plus pcb parasitics and optional external load capacitors. if a crystal designed to oscillate with a dif- ferent load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. a crystal designed to operate at a higher load capacitance than the value specified for the oscillator is always pulled higher in fre- quency. adding capacitance to increase the load capacitance on the crystal increases the start-up time and can prevent oscillation altogether. in actuality, the oscillator pulls every crystal. the crys- tals natural frequency is below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified fre- quency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: fp is the amount the crystal frequency is pulled in ppm c m is the motional capacitance of the crystal c case is the case capacitance c spec is the specified load capacitance c load is the actual load capacitance when the crystal is loaded as specified (i.e., c load = c spec ), the frequency pulling equals zero. communication protocol the max7057 registers are programmed through an spi interface. figure 2 shows the timing diagram of the spi. the gpo must be properly configured to act as an spi data output (sdo) by setting the configuration 1 register (see tables 2, 3, 15, and 16). the spi operates on a byte format, according to figure 2. f c cccc p m case load case spec = ++ ? ? ? ? ? ? ? 2 11 10 6 f f decimal value to program rf xtal -16 transmit frequency registers ? ? ? ? ? ? = 4096 300mhz to 450mhz frequency-programmable ask/fsk transmitter 10 ______________________________________________________________________________________ depending on the command, byte 1 through byte n may assume different functions. they may either be a direct command (write, read, read all, reset), or an address or data contents. the commands available in the max7057 spi are described in detail below: write: the write command (0x01) is used to program the max7057 registers (see tables 2 and 3). the for- mat shown in figure 3 must be followed, allowing all the registers to be programmed within one cs cycle. using a byte descriptive notation, the write command can be viewed as the following sequence: data 0 is then written to the register addressed by max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 12 ______________________________________________________________________________________ using a byte descriptive notation, the read command can be viewed as the following sequence, within the same cs cycle: with this command, all the registers can be read within the same cycle of cs . the addresses can be given in any order. read-all: to execute an spi read-all operation, gpo must be configured to either a ckout_sdo or sdo function (see tables 15 and 17 for details). using a byte descriptive notation, the read command can be viewed as the following sequence, within two cs cycles: reset: the max7057 can be reset to its power-up state through the reset command. figure 4. spi read command format read all command (0x03) address n a7 a6 a5 a4 a3 a2 a1 a0 d7 d7 d7 d6 d5 d4 d3 d2 d1 d0 d0 d0 gpo sdi sclk cs data n data n + 1 data n + n gpo sdi sclk cs d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 a7 a7 d7 d7 a6 a5 a4 a3 a2 a1 a0 a0 d0 d0 read command (0x02) address 0 address 1 0x00 address n data n - 1 data 0 data n figure 5. spi read-all command format sdi : <0x02> using a byte descriptive notation, the reset command can be viewed as the following sequence, within the same cs cycle: sdi: <0x04> features and settings values and parameters are set through registers in the max7057 that are addressable through the spi. these registers contain bits that either turn functions on and off or program numerical settings. the following set- tings are controlled through the spi. variable capacitor the internal variable shunt capacitor, which is instru- mental in matching the pa to the antenna, is controlled by setting 5 bits in the configuration 0 register. this allows for 32 levels of shunt capacitance control. since the control of these 5 bits is independent of the other settings, any capacitance value can be chosen at any frequency, making it possible to maintain maximum transmitter efficiency while moving rapidly from one fre- quency to another. clock output the max7057 has a buffered clock output that can serve as a clock for a microprocessor. the divide ratio is set through the configuration 0 register (see tables 5 and 6). the divide settings are 1 (no division), 2, 4, 8, or 16; the original undivided frequency is based on the reference frequency generated by the external crystal. the buffered clock output is available at gpo when enabled by setting the configuration 1 register (see tables 2, 3, 15, and 16). mode select and crystal shutdown the transmission mode is selected by writing to a regis- ter. the default mode is ask and the mode can be changed to fsk by writing a 1 to the mode bit in the control register. this register is also used to keep the crystal circuit powered up in the shutdown mode. registers the following tables provide information on the max7057 registers. max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter ______________________________________________________________________________________ 13 sdi sclk cs reset command (0x04) address register name description 0x00 contrl control register. controls the mode (ask/fsk), crystal clock output, envelope-shaping, pll bandwidth, and spi enable. 0x01 config0 configuration 0 register. controls the capacitance at the pa output and clock output frequency divider. 0x02 hifreq1 high-frequency 1 register (upper byte). sets the high frequency in fsk transmission. 0x03 hifreq0 high-frequency 0 register (lower byte). sets the high frequency in fsk transmission. 0x04 lofreq1 low-frequency 1 register (upper byte). sets the low frequency in fsk transmission, or carrier frequency in ask transmission. 0x05 lofreq0 low-frequency 0 register (lower byte). sets the low frequency in fsk transmission, or carrier frequency in ask transmission. 0x06 fload frequency load register. performs the frequency load function. 0x07 datain data in register. spi equivalent of din pin. 0x08 en enable register. spi equivalent of enable pin. 0x09 config1 configuration 1 register. gpo selector. 0x0c status status register. figure 6. reset command format table 2. register summary max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 14 ______________________________________________________________________________________ bit name function 4-0 cap[4:0] 5-bit capacitor setting 7-5 ckdiv[2:0] 3-bit clock output frequency divider table 5. configuration 0 register (address: 0x01) data name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode contrl 0x00 0 0 spioffsht pllbw shape ckouts ckouton mode r/w config0 0x01 ckdiv[2] ckdiv[1] ckdiv[0] cap[4] cap[3] cap[2] cap[1] cap[0] r/w hifreq1 0x02 fhi[15] fhi[14] fhi[13] fhi[12] fhi[11] fhi[10] fhi[9] fhi[8] r/w hifreq0 0x03 fhi[7] fhi[6] fhi[5] fhi[4] fhi[3] fhi[2] fhi[1] fhi[0] r/w lofreq1 0x04 flo[15] flo[14] flo[13] flo[12] flo[11] flo[10] flo[9] flo[8] r/w lofreq0 0x05 flo[7] flo[6] flo[5] flo[4] flo[3] flo[2] flo[1] flo[0] r/w fload 0x06 fload r/w datain 0x07 datain_bit r/w en 0x08 enable_bit r/w config1 0x09 0 0 0 0 0 gposel[2] gposel[1] gposel[0] r/w status 0x0c fhi/lo[15] fhi/lo[14] fhi/lo[13] fhi/lo[12] x 0 txready noxtal r table 3. register configuration bit name function 0 mode ask(0) or fsk(1) 1 ckouton crystal clock output enable(1) on gpo output 2 ckouts crystal clock output enable(1) while part is in shutdown mode 3 shape disable(0) or enable(1) transmitter envelope-shaping resistor 4 pllbw pll bandwidth setting, low(0) = 300khz or high(1) = 600khz; 300khz is recommended for fractional-n and 600khz for fixed-n 5 spioffsht enable(0) or disable(1) spi communication during shutdown table 4. control register (address: 0x00) the 4 msbs of hifreq1 (fhi[15:12]) are the integer portion of the divider, excluding offset of 16. the 12 lsbs (fhi[11:0]) are the fractional part of the divider. max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter ______________________________________________________________________________________ 15 decimal binary crystal frequency divided by 0 000 1 1 001 2 2 010 4 3 011 8 4-7 1xx 16 table 6. ckdiv[2:0] of configuration 0 register (address: 0x01) bit name function 7-0 fhi[15:8] 8-bit upper byte of high-frequency divider for fsk table 7. high-frequency 1 register (address: 0x02) bit name function 7-0 fhi[7:0] 8-bit lower byte of high-frequency divider for fsk table 8. high-frequency 0 register (address: 0x03) bit name function 7-0 flo[15:8] 8-bit upper byte of low-frequency divider for fsk/ask table 9. low-frequency 1 register (address: 0x04) bit name function 7-0 flo[7:0] 8-bit lower byte of low-frequency divider for fsk/ask table 10. low-frequency 0 register (address: 0x05) decimal value fhi[15:12], flo[15:12] fhi[11:0], flo[11:0] 12.0220 0xc 0x05a 2.9536 0x2 0xf42 table 11. maximum and minimum values for frequency divide the 4 msbs of lofreq1 (flo[15:12]) are the integer portion of the divider, excluding offset of 16. the 12 lsbs (flo[11:0]) are the fractional part of the divider. valid values for the divider are shown in table 11. max7057 these values are internally summed with 16, and thus, the min and max divider becomes approximately 19 and 28. these limits must be followed, to prevent the delta-sigma number generator from overflowing. whenever all of the fhi[11:0] and flo[11:0] are zero, only an integer divider is used, and the delta-sigma modula- tor is not in operation. this allows lower current opera- tion. the 600khz pll bandwidth could be used in this mode to reduce phase noise. 300mhz to 450mhz frequency-programmable ask/fsk transmitter 16 ______________________________________________________________________________________ bit name function 0 fload effectively changes the pll frequency to the ones written in registers 2C5. this is a self-reset bit, and is reset to zero after the operation is completed. table 12. frequency load register (address: 0x06) bit name function 0 datain_bit spi equivalent of din, where the transmitted data can be controlled through the spi interface. it should be kept low (0) if only the external din pin is used. the external din pin should also be kept low (0) if the spi datain_bit is used. table 13. data in register (address: 0x07) bit name function 0 enable_bit spi equivalent of enable. it should be kept low (0) if the external enable pin is used. the external enable pin should also be kept low (0) if the spi enable_bit is used. table 14. enable register (address: 0x08) bit name function 2-0 gposel[2:0] 3-bit gpo selector 7-3 reserved 0 reserved. set to 0 for normal operation. table 15. configuration 1 register (address: 0x09) decimal binary gpo description 0 000 ckout_sdo clock/sdo output. outputs clock when cs is high and clock output is enabled; outputs sdo when cs is low. 1 001 sdo spi serial data output (sdo) 2 010 ckout clock output 3 011 reserved reserved 4 100 reserved reserved 5 101 noxtal internal crystal oscillator status. high means oscillator is not in operation. 6 110 txready transmitter ready status. high means pll is locked and max7057 is ready to transmit data. 7 111 datain_bit a copy of datain_bit table 16. general-purpose output selector (gposel[2:0]) for configuration 1 register applications information output matching to 50 ? when matched to a 50 ? system, the max7057s pa is capable of delivering +9.2dbm of output power at pavdd = +2.7v with a broadband match. the output of the pa is an open-drain transistor, which has internal selectable shunt tuning capacitors (see the variable capacitor section) for impedance matching. it is con- nected to pavdd or rout through a pullup inductor for proper biasing. the internal selectable shunt capac- itors make it easy for tuning when changing the output frequency. the pullup inductor from the pa to pavdd or rout serves three main purposes: resonating the capacitive pa output, providing biasing for the pa, and acting as a high-frequency choke to prevent rf energy from coupling onto the supply voltage. the pi network between the pa output and the antenna also forms a lowpass filter that provides attenuation for the higher- order harmonics. output matching to pcb loop antenna in many applications, the max7057 must be imped- ance-matched to a small-loop antenna. the antenna is usually fabricated out of a copper trace on a pcb in a rectangular, circular, or square pattern. the antenna has an impedance that consists of a lossy component and a radiative component. to achieve high radiating efficiency, the radiative component should be as high as possible, while minimizing the lossy component. in addition, a loop antenna has an inherent loop induc- tance associated with it (assuming the antenna is termi- nated to ground). in a typical application, the inductance of the loop antenna is approximately 50nh to 100nh. the radiative and lossy impedances can be anywhere from a few tenths of an ohm to 5 ? or 10 ? . layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. at high-frequency inputs and out- puts, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. at high frequencies, trace lengths that are in the order of /10 or longer act as antennas, where is the wave- length. keeping the traces short also reduces parasitic induc- tance. generally, 1in of pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace con- necting to a 100nh inductor adds an extra 10nh of inductance, or 10%. to reduce parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. using a solid ground plane can reduce the parasitic inductance from approximately 20nh/in to 7nh/in. also, use low-inductance connections to the ground plane, and place decoupling capacitors as close as possible to all v dd pins. max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter ______________________________________________________________________________________ 17 bit name function 0 noxtal internal crystal oscillator status. high means oscillator is not in operation. 1 txready transmitter ready status. high means pll is locked and max7057 is ready to transmit data. 2 reserved 0 reserved. set to 0 for normal operation. 3 x reserved 7-4 fhi/lo[15]Cfhi/lo[12] ask mode: outputs flo[15:12]. fs k m od e: w hen d atai n p i n/b i t i s hi g h, outp uts fhi [ 15:12] ; w hen d atai n p i n/b i t i s l ow , outp uts fl o[ 15:12] . table 17. status register (address: 0x0c) max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter 18 ______________________________________________________________________________________ max7057 c12 c13 c11 16 dvdd 15 gpo 14 dgnd 13 din 12 enable 11 agnd gpo din enable sclk sdi cs v dd c6 c7 c4 c5 c2 7 pavdd v dd c9 c8 c15 c14 xtal1 y1 10 c10 xtal2 9 v dd avdd 8 r1 l2 6 rout l1 c1 5 paout c3 rf out 4 pagnd 3 sclk cs 1 2 sdi typical application circuit component list designation qty description c1, c2 1 10pf 5%, 50v c0g ceramic capacitors (0603) murata grm1885c1h100j c3 1 6.8pf 5%, 50v c0g ceramic capacitor (0603) murata grm1885c1h6r8j c4, c7 2 220pf 5%, 50v c0g ceramic capacitors (0603) murata grm1885c1h221j c5 1 680pf 5%, 50v c0g ceramic capacitor (0603) murata grm1885c1h681j c6, c9, c12 3 10nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h103k c8, c13 2 100nf 10%, 50v x7r ceramic capacitors (0603) murata grm188r71h104k c10, c11 2 100pf 5%, 50v c0g ceramic capacitors (0603) murata grm1885c1h101j c14, c15 2 4pf 5%, 50v c0g ceramic capacitors (0603) murata grm1885c1h4r0c l1 1 22nh 5% wire-wound inductor (0603) murata lqw18an22nj00 l2 1 13nh 5% wire-wound inductor (0603) murata lqw18an13nj00 r1 1 0 ? resistor (0603) y1 1 16mhz crystal crystek 17466, suntsu scx284 max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter ______________________________________________________________________________________ 19 max7057 9 10 1 pfd vco serial interface and digital control delta-sigma modulator frequency divider crystal oscillator envelope shaping charge pump loop filter xtal2 7 pav dd 8 av dd xtal1 pa cs 2 sdi 16 11 dv dd 3 sclk 5 6 paout 4 pagnd rout agnd 12 enable 13 din 14 dgnd 15 gpo functional diagram chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 so s16+3 21-0041 90-0097 max7057 300mhz to 450mhz frequency-programmable ask/fsk transmitter maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/08 initial release 1 4/11 added reflow soldering information to absolute maximum ratings , added bandwidth notation to toc21, and corrected spi format in figure 2 2, 7, 11 |
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